[PDF] EE8351 Digital Logic Circuits (DLC) 2017 Regulation Syllabus, Notes and Multiple Choice Questions for Anna University Students
Last updated on Sep 4, 2023
Syllabus
EE8351 Digital Logic Circuits
- UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES:Review of number systems, binary codes, error detection and correction codes (Parity and Hamming code) - Digital Logic Families -comparison of RTL, DTL, TTL, ECL and MOS families -operation, characteristics of digital logic family.
- UNIT II COMBINATIONAL CIRCUITS:Combinational logic - representation of logic functions-SOP and POS forms, K-maprepresentations - minimization using K maps - simplification and implementation ofcombinational logic – multiplexers and de multiplexers - code converters, adders,subtractors, Encoders and Decoders.
- UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS:Sequential logic- SR, JK, D and T flip flops - level triggering and edge triggering - counters -asynchronous and synchronous type - Modulo counters - Shift registers - design ofsynchronous sequential circuits – Moore and Melay models- Counters, state diagram; statereduction; state assignment.
- UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABILITY LOGIC DEVICES :Asynchronous sequential logic circuits-Transition tability, flow tability-race conditions,hazards &errors in digital circuits; analysis of asynchronous sequential logic circuitsintroduction to Programmability Logic Devices: PROM – PLA –PAL, CPLD-FPGA.
- UNIT V VHDL:RTL Design – combinational logic – Sequential circuit – Operators – Introduction toPackages – Subprograms – Test bench. (Simulation /Tutorial Examples: adders, counters, flip flops, Multiplexers & De multiplexers).
